Verilator
| Verilator | |
|---|---|
 | |
| Developer | Wilson Snyder |
| Stable release | 5.052 
/ 5 September 2026 |
| Written in | C++ |
| Operating system | Linux, FreeBSD, Microsoft Windows (via Cygwin or WSL) |
| Type | Simulator |
| License | LGPL 3.0 only, or Artistic 2.0 |
| Website | verilator |
| Repository | |
Verilator is a software programming tool which converts the hardware description language Verilog to a cycle-accurate behavioral model in the programming languages C++ or SystemC. The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free electronic design automation (EDA) software. It is free and open-source software released under a GNU Lesser General Public License (LGPL) 3.0 only, or an Artistic License 2.0.