ARM Cortex-A53
 | |
| General information | |
|---|---|
| Launched | 2012 |
| Designed by | ARM Holdings |
| Performance | |
| Max. CPU clock rate | 400 MHz to 2.30 GHz |
| FSB speeds | 100 MHz to 118 MHz OC |
| Physical specifications | |
| Cores |
|
| Cache | |
| L1 cache | 8–64 KiB |
| L2 cache | 128 KiB – 2 MiB |
| Architecture and classification | |
| Instruction set | ARMv8-A |
| Products, models, variants | |
| Product code name |
|
| History | |
| Predecessor | ARM Cortex-A7 |
| Successor | ARM Cortex-A55 |
The ARM Cortex-A53 is one of the first two central processing units implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre, along with the Cortex-A57. The Cortex-A53 is a two-wide in-order superscalar processor, capable of dual-issuing some instructions. It was announced October 30, 2012 and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration. It is available as an IP core to licensees, like other ARM intellectual property and processor designs.