ARM Cortex-A520
| General information | |
|---|---|
| Launched | 2023 |
| Designed by | ARM Ltd. |
| Performance | |
| Max. CPU clock rate | 1.8 GHz to 2.27 GHz |
| Cache | |
| L1 cache | 64/128 KiB (32/64 KiB I-cache with parity, 32/64 KiB D-cache) per core |
| L2 cache | 0–512 KiB per complex |
| L3 cache | 256 KiB – 32 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-A520 |
| Instruction set | ARMv9.2-A |
| Products, models, variants | |
| Product code name |
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| History | |
| Predecessor | ARM Cortex-A510 |
| Successor | ARM C1-Nano |
The ARM Cortex-A520 is a CPU microarchitecture designed by Arm Holdings and licensed as a semiconductor intellectual property core. It implements the 64-bit ARMv9 instruction set and supports heterogeneous computing via a big.LITTLE configuration. The design succeeds the Cortex-A510 in its role as a low performance, power efficient core, and is announced in 2023 together with the Cortex-A720 and the X4.